1. Field of the Invention
The invention relates to a method of controlling a clock signal in a circuit receiving an external clock signal and transmitting an internal clock signal. The invention relates also to a circuit for controlling a clock signal.
2 Description of the Related Art
A circuit for controlling a clock signal is generally comprised of a feedback system synchronization circuit such as phase locked loop, and is presently requested to eliminate clock skew in short synchronization time.
In order to meet with such request, a lot of circuits have been suggested in the following documents, for instance:
(a) Japanese Unexamined Patent Publication No. 8-237091 PA1 (b) 1996 Symposium on VLSI Circuit, pp. 112-113 PA1 (c) 1996 Symposium on VLSI Circuit, pp. 192-193 PA1 (d) Proceedings of IEEE 1992 CICC 25.2 PA1 (e) IEICE TRANS. ELECTRON, Vol. E79-C, No. Jun. 6, 1996 pp. 798-807 PA1 (i) Japanese Unexamined Patent Publication No. 5-152438 PA1 (g) Japanese Unexamined Patent Publication No. 6-244282
FIGS. 1 to 6A and 6B illustrate circuits suggested in the above-listed prior art (a) to (e), respectively. As mentioned later in detail, the above-mentioned documents (a) to (g) do not suggest detecting clock delay unlike the present invention.
FIG. 1 illustrates a synchronization delay circuit having been suggested in Japanese Unexamined Patent Publication No. 8-237091.
The illustrated synchronization delay circuit is comprised of a synchronization delay circuit macro 908, an input buffer 903, a dummy delay circuit 905, and a clock driver 904. The synchronization delay circuit macro 908 is comprised of a first row of delay circuits 901 for measuring a time difference, and a second row of delay circuits 902 for reproducing the thus measured delay time. A clock signal is transmitted in the second row of delay circuits 902 in a direction opposite to a direction in which a clock signal is transmitted in the first row of delay circuits 901. The dummy delay circuit 905 is designed to have delay time equal to a sum (td1+td2) of delay time td1 of the input buffer 903 and delay time td2 of the clock driver 904.
The dummy delay circuit 905 is usually comprised of an input buffer dummy 905A having the same structure and hence the same delay time as that of the input buffer 903, and a clock driver dummy 905B, in order to equalize the delay time thereof to a sum (td1+td2) of the delay time td1 of the input buffer 903 and delay time td2 of the clock driver 904.
An external clock signal 906 is input into the first row of delay circuits 901 through the input buffer 903 and the dummy delay circuit 905, and output through the second row of delay circuits 902. The thus output clock signal is driven by the clock driver 904 to thereby turn into an internal clock signal 907, which is transmitted to internal circuits (not illustrated).
With reference to FIG. 1, the first row of delay circuits 901 has the same delay time as that of the second row of delay circuits 902. The first row of delay circuits 901 measures a certain period of time, and the second row of delay circuits 902 reproduces the thus measured period of time. A signal input into the first row of delay circuits 901 is advanced through the first row of delay circuits 901 by a desired period of time, and then, a signal is advanced in the second row of delay circuits 902 through the same number of delay devices as the number of delay devices through which the signal has passed in the first row of delay circuits 901. As a result, the second row of delay circuits 902 can reproduce a period of time having been measured by the first row of delay circuits 901.
Processes by which a signal is advanced in the second row of delay circuits 902 through the same number of delay devices as the number of delay devices through which the signal has passed in the first row of delay circuits 901 is grouped into two groups with respect to a direction or directions in which a signal is transmitted in the first and second rows of delay circuits 901 and 902. In addition, a length of the second row of delay circuits 902 is determined either by selecting an end of the length or by entirely selecting a row. Hence, the above-mentioned processes can be grouped into four groups.
For instance, as to the former grouping, each of FIGS. 4 and 5 illustrates a circuit in which a clock signal is advanced in the first row of delay circuits 901 in the same direction as a direction in which a clock signal is advanced in the second row of delay circuits 902, and the number of elements constituting the second row of delay circuits 902 is determined by an output terminal of the second row of delay circuits 902. Each of FIGS. 2 and 3 illustrates a circuit in which a clock signal is advanced in the first row of delay circuits 901 in a direction opposite to a direction in which a clock signal is advanced in the second row of delay circuits 902, and the number of elements constituting the second row of delay circuits 902 is determined by an input terminal of the second row of delay circuits 902.
As to the latter grouping, each of FIGS. 2 and 5 illustrates a circuit in which a length of the second row of delay circuits 902 is determined by selecting an end of the length, whereas each of FIGS. 3 and 4 illustrates a circuit in which a length of the second row of delay circuits 902 is determined by selecting an entire length.
FIG. 2 illustrates a circuit having been suggested in the above-listed document (a), FIG. 3 illustrates a circuit having been suggested in the above-listed document (e), FIG. 4 illustrates a circuit having been suggested in the above-listed document (c), and FIG. 5 illustrates a circuit having been suggested in the above-listed documents (b) and (d).
Hereinbelow is explained an operation for removing clock skew with reference to timing charts illustrated in FIGS. 6A, 6B, 7A, and 7B. (A) Clock delay in a circuit having no synchronization delay circuits
FIG. 6A illustrates a circuit having no synchronization delay circuits. An external clock signal 906 is input through an input buffer 903, and is driven by a clock driver 904 to thereby turn into an internal clock signal 907. A delay time difference between the external clock signal 906 and the internal clock signal 907 is equal to a sum of delay time td1 of the input buffer 903 and delay time td2 of the clock driver 904. As illustrated in FIG. 6B, the sum (td1+td2) is clock skew in the illustrated circuit. (B) Principle in removal of clock delay by means of a synchronization delay circuit
A synchronization delay circuit removes clock skew, based on that a clock pulse is input thereinto every clock cycle tCK. Specifically, a delay circuit having delay time defined as (tCK-(td1+td2)) is positioned between an input buffer having delay time td1 and a clock driver having delay time td2, and is designed to have delay time equal to a clock cycle tCK (td1+tCK-(td1+td2)+td2 =tCK). As a result, an internal clock signal transmitted from the clock driver has the same timing as that of an external clock signal. (C) Removal of clock delay by means of a synchronization delay circuit
FIG. 7B is a timing chart of a synchronization delay circuit.
A synchronization delay circuit needs 2 clock cycles (2.times.tCK) to operate. In a first cycle, a synchronization delay circuit measures delay time (tCK (td1+td2)) dependent on a clock cycle, and determines delay for a delay circuit which reproduces delay time (tCK-(td1+td2)). In a second cycle, the thus measured delay time (tCK-(td1+td2)) is used.
As illustrated in FIG. 7A, a dummy delay circuit 905 and a row of delay circuits 901 are used for measuring the delay time (tCK-(td1+td2)) dependent on a clock cycle, in the first cycle.
A first pulse in successive two pulses in an external clock signal 906 is input through an input buffer 903, and is transmitted through a dummy delay circuit 905 and a row of delay circuits 901 during a clock cycle tCK starting when the first pulse leaves the input buffer 903 and terminating when a second pulse leaves the input buffer 903. Since the dummy delay circuit 905 has delay time defined as (td1+td2), a period of time in which the external clock signal 906 is advanced through a first row of delay circuits 901 is defined as (tCK-(td1+td2)).
A second row of delay circuits 902 is designed to have delay time equal to the above-mentioned period of time (tCK-(td1+td2)) in which the external clock signal 906 is advanced through the first row of delay circuits 901.
The delay time of the second row of delay circuits 902 can be set in accordance with any one of the above-mentioned four processes.
In the second cycle, a clock signal transmitted from the input buffer 930 advances through the second row of delay circuits 902 having delay time defined as (tCK-(td1+td2)), and then, is output through the clock driver 904. Thus, there is produced an internal clock signal 907 having delay time tCK.
The thus produced internal clock signal 907 has a cycle of 2.times.tCK and has no clock skew.
However, the above-mentioned synchronization delay circuits are accompanied with the following problems.
The first problem is that since dummy delay of a clock signal is fixed, it is necessary to estimate fixed dummy delay in advance. It would be possible to design a dummy delay circuit for each one of chips in a device in which clock delay can be estimated in advance, such as a micro-processor and a memory device. However, it would be quite difficult to design a dummy delay circuit for such a device in which clock delay is dependent on wiring layout of a chip, as an application specific integrated circuit (ASIC).
The second problem is that, as illustrated in FIGS. 8A and 8B, there is a difference both in dependency of delay time on a temperature and in dependency of delay time on a source voltage between a clock driver and a clock driver dummy, and in addition, even in a device in which clock delay can be estimated in advance, such as a micro-processor and a memory device.
The third problem is that it is impossible to eliminate a delay time difference in an internal clock signal made synchronized with an external clock signal, as having been indicated in the above-mentioned document (e), because a delay circuit for measuring a delay difference and a delay circuit for reproduction are both accomplished by determining the number of stages in a delay circuit row, and further because there is a time difference in a period of time for charging and discharging between those delay circuits. This causes dependency of a delay error or a delay time difference inherent to a digital circuit, on a clock cycle.
The fourth problem is that it is necessary to entirely drive a row of delay circuits when a clock cycle is to be reproduced by means of the row of delay circuits, resulting in an increase in load capacity and an increase in current consumption.